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| Freescale Semiconductor Advance Information www..com Document Number: MC10XS3412 Rev. 8.0, 10/2008 Quad High Side Switch (Dual 10m, Dual 12m) The 10XS3412 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(ON) MOSFETs (dual 10m/dual 12m) can control four separate 55W / 28W bulbs, and/or Xenon modules, and/or LEDs. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XS3412 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide failsafe functionality of the outputs in case of MCU damaged. Features * Four protected 10m and 12m high side switches (at 25C) * Operating voltage range of 6.0V to 20V with sleep current < 5.0A, extended mode from 4.0V to 28V * 8MHz 16-bit 3.3V and 5V SPI control and status reporting with daisy chain capability * PWM module using external clock or calibratable internal oscillator with programmable outputs delay management * Smart over-current shutdown, severe short-circuit, overtemperature protections with time limited autoretry, and fail-safe mode in case of MCU damage * Output OFF or ON open-load detection compliant to bulbs or LEDs and short to battery detection. Analog current feedback with selectable ratio and board temperature feedback. 10XS3412 HIGH SIDE SWITCH PNA SUFFIX (PB-FREE) 98ARL10596D 24-PIN PQFN ORDERING INFORMATION Device MC10XS3412CPNA Temperature Range (TA) - 40C to 125C Package 24 PQFN VDD VDD VPWR VDD VPWR 10XS3412 VDD I/O SCLK CS SI I/O MCU SO I/O I/O I/O I/O A/D GND WAKE FS SCLK CS SO RST SI IN0 IN1 IN2 IN3 CSNS FSI GND VPWR HS0 LOAD HS1 LOAD HS2 LOAD HS3 LOAD Figure 1. 10XS3412 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM www..com VDD VPWR IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3 VDD Failure Detection Internal Regulator VREG POR Over/Under-voltage Protections Charge Pump VPWR Voltage Clamp Selectable Slew Rate Gate Driver Selectable Over-current Detection Severe Short-circuit Detection Short to VPWR Detection Over-temperature Detection Open-load Detections HS0 Logic HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator VREG PWM Module HS1 HS2 HS2 HS3 FSI Programmable Watchdog Temperature Feedback Over-temperature Prewarning Analog MUX VDD HS3 Selectable Output Current Recopy GND CSNS Figure 2. 10XS3412 Simplified Internal Block Diagram 10XS3412 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS www..com PIN CONNECTIONS Transparent Top View of Package WAKE CSNS 1 24 14 GND 23 FSI GND 22 HS2 Definition This pin reports an analog value proportional to the designated HS[0:3] output current or the temperature of the GND flag (pin 14). It is used externally to generate a ground-referenced voltage for the microcontroller (MCU) . Current recopy and temperature feedback is SPI programmable. Each direct input controls the device mode. The IN[0 : 3] high side input pins are used to directly control HS0 : HS3 high side output pins. The PWM frequency can be generated from IN0 pin to PWM module in case of external clock is set. Output Input Input Input Input Input Power Fault Status (Active Low) Wake Reset Chip Select (Active Low) Serial Clock Serial Input Digital Drain Voltage This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. This input pin controls the device mode. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep Mode. This input pin is connected to a chip select output of a master microcontroller (MCU). This input pin is connected to the MCU providing the required bit shift clock for SPI communication. This pin is a command data input pin connected to the SPI serial data output of the MCU or to the SO pin of the previous device of a daisy-chain of devices. This pin is an external voltage input pin used to supply power interfaces to the SPI bus. SCLK VDD RST IN3 IN2 IN1 3 13 12 11 10 SO GND 16 17 9 8 7 6 5 4 HS3 18 15 VPWR 19 HS1 20 NC 21 HS0 Figure 3. 10XS3412 Pin Connections Table 1. 10XS3412 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Pin Number 1 Pin Name CSNS Pin Function Output Formal Name Output Current Monitoring 2 3 5 6 7 8 9 10 11 12 13 IN0 IN1 IN2 IN3 FS WAKE RST CS SCLK SI VDD Input Direct Inputs IN0 2 NC CS FS SI 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS www..com Table 1. 10XS3412 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Pin Number 14, 17, 23 15 16 18 19 21 22 4, 20 24 Pin Name GND VPWR SO HS3 HS1 HS0 HS2 NC FSI Pin Function Ground Power Output Output Formal Name Ground Definition These pins, internally shorted, are the ground for the logic and analog circuitry of the device. These ground pins must be also shorted in the board. Positive Power Supply This pin connects to the positive power supply and is the source of operational power for the device. Serial Output High Side Outputs This output pin is connected to the SPI serial data input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. Protected 10m (HS0 and HS1) 12m (HS2 and HS3) high side power output pins to the load. N/A Input No Connect Fail-Safe Input These pins may not be connected. This input enables the watchdog timeout feature. 10XS3412 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS www..com ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS VPWR Supply Voltage Range Load Dump at 25C (400ms) Maximum Operating Voltage Reverse Battery at 25C (2 min.) VDD Supply Voltage Range Input / Output Voltage WAKE Input Clamp Current CSNS Input Clamp Current HS [0:3] Voltage Positive Negative Output Current(1) Method(2) IHS[0:3] ECL [0:3] VESD1 VESD2 VESD3 VESD4 VDD (4) Symbol Value Unit VPWR(SS) 41 28 -18 -0.3 to 5.5 -0.3 to VDD + 0.3 2.5 2.5 V V V mA mA V ICL(WAKE) ICL(CSNS) VHS[0:3] 41 -16 6 100 A mJ V 8000 2000 750 500 Output Clamp Energy Using Single-Pulse ESD Voltage (3) Human Body Model (HBM) for HS[0:3], VPWR and GND Human Body Model (HBM) for other pins Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature C TA TJ TSTG - 40 to 125 - 40 to 150 - 55 to 150 C Notes 1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 2. Active clamp energy using single-pulse method (L = 2mH, RL = 0, VPWR = 14V, TJ = 150C initial). 3. 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500), the Machine Model (MM) (CZAP = 200pF, RZAP = 0), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). Input / Output pins are: IN[0:3], RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS www..com Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings THERMAL RESISTANCE Thermal Resistance(5) Junction to Case Junction to Ambient Peak Pin Reflow Temperature During Solder Mounting(6) RJC RJA TSOLDER <1.0 30 245 Symbol Value Unit C/ W C Notes 5. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 C/W of RJA can be reached in a real application case (4 layers board). 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 10XS3412 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic POWER INPUTS Battery Supply Voltage Range Fully Operational Extended mode(7) Battery Clamp Voltage (8) Symbol Min Typ Max Unit VPWR 6.0 4.0 VPWR(CLAMP ) V - - 47 20 28 53 V mA - 6.5 20 mA - 6.5 8.0 A 41 VPWR Operating Supply Current Outputs commanded ON, HS[0 : 3] open, IN[0:3] > VIH VPWR Supply Current Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0 : 3] shorted to the ground with VDD= 5.5V WAKE > VIH or RST > VIH and IN[0:3] < VIL Sleep State Supply Current VPWR = 12V, RST = WAKE = IN[0:3] < VIL, HS[0 : 3] shorted to the ground TA = 25C TA = 85C VDD Supply Voltage VDD Supply Current at VDD = 5.5V No SPI Communication 8.0MHz SPI Communication(9) VDD Sleep State Current at VDD = 5.5V Over-voltage Shutdown Threshold Over-voltage Shutdown Hysteresis Under-voltage Shutdown Threshold(10) VPWR and VDD Power on Reset Threshold Recovery Under-voltage Threshold VDD Supply Failure Threshold ( for VPWR > VPWR(UV) ) IPWR(ON) IPWR(SBY) IPWR(SLEEP) - - VDD(ON) IDD(ON) - - IDD(SLEEP) VPWR(OV) VPWR(OVHYS ) 1.0 - - 5.0 30 5.5 V mA 3.0 1.6 5.0 - 32 0.8 3.9 4.1 2.5 2.2 - 5.0 36 1.5 4.3 0.9 4.5 2.8 A V V V VPWR(UV) V V - 28 0.2 3.3 0.5 3.4 2.2 VPWR(UV) VSUPPLY(PO R) Vpwr(UV)_U P VDD(FAIL) Notes 7. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0V to 6.0V voltage range, the device is only protected with the thermal shutdown detection. 8. Measured with the outputs open. 9. Typical value guaranteed per design. 10. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the VPWR degradation level did not go below the under-voltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic OUTPUTS HS0 TO HS3 HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 25C) VPWR = 4.5V VPWR = 6.0V VPWR = 10V VPWR = 13V HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 150C) VPWR = 4.5V VPWR = 6.0V VPWR = 10V VPWR = 13V HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0A, VPWR = -18V)(11) RSD_01(ON) TA = 25C TA = 150C HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 25C) VPWR = 4.5V VPWR = 6.0V VPWR = 10V VPWR = 13V HS[2,3] Output Drain-to-Source ON Resistance (IHS = 5.0A, TA = 150C) VPWR = 4.5V VPWR = 6.0V VPWR = 10V VPWR = 13V HS[2,3] Output Source-to-Drain ON Resistance (IHS = -5.0AVPWR = -18V)(11) RSD_23(ON) TA = 25C TA = 150C Maximum Severe Short-Circuit Impedance Detection(12) RSHORT - - 28 - - 64 18 24 100 m RDS_23(ON) - - - - - - - - 75 33 21 21 m RDS_23(ON) - - - - - - - - 44 19 12 12 m - - - - 15 20 m RDS_01(ON) - - - - - - - - 62 27 17 17 m RDS_01(ON) - - - - - - - - 36 16 10 10 m m Symbol Min Typ Max Unit Notes 11. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 12. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design. 10XS3412 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Output Over-current Detection Levels (6.0V < VHS[0:3] < 20V) 28W bit = 0 OCHI1_0 OCHI2_0 OC1_0 OC2_0 OC3_0 OC4_0 OCLO4_0 OCLO3_0 OCLO2_0 OCLO1_0 28W bit = 1 OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 Current Sense Ratio (6.0V < HS[0:3] < 20V, CSNS < 28W bit = 0 CSNS_ratio bit = 0 CSNS_ratio bit = 1 28W bit = 1 CSNS_ratio bit = 0 CSNS_ratio bit = 1 Current Sense Ratio (CSR0) Accuracy (6.0V < VHS[0:3] < 20V) with 28W bit=0 Output Current 12.5A 5.0A 3.0A 1.5A Notes 13. Current sense ratio = ICSNS / IHS[0:3] CSR0_0 CSR1_0 CSR0_1 CSR1_1 CSR0_0_ACC -12 -13 -16 -20 - - - - 12 13 16 20 - - - - 1/8700 1/53000 1/4350 1/26500 - - - - % 5.0V)(13) 78 50 44.1 37.8 31.5 25.2 18.9 12.6 10.0 6.4 39 25 22.0 18.9 15.7 12.6 9.4 6.0 4.5 3.0 94.0 60.0 52.5 45.0 37.5 30.0 22.5 15.0 12.0 8.0 47.0 30.0 26.2 22.5 18.7 15.0 11.2 7.5 6.0 4.0 110 70 60.9 52.2 43.5 34.8 26.1 17.4 14.0 9.6 55 35 30.5 26.1 21.8 17.4 13.1 9.0 7.5 5.0 - Symbol Min Typ Max Unit A 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Current Sense Ratio (CSR0) Accuracy (6.0V < VHS < 20V) with 28W bit=1 Output Current 3.0A 1.5A CSR0 Current Recopy Accuracy with one calibration point (6.0V < VHS[0:3] < 20V)(14) Output Current 5.0A Notes 14. Based on statistical analysis. It is not production tested. CSR0_0_ACC( CAL) Symbol CSR0_1_ACC Min Typ Max Unit % -16 -20 -5.0 - - - 16 20 5.0 % 10XS3412 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic OUTPUTS HS0 TO HS3 (continued) CSR0 Current Recopy Temperature Drift (6.0V < VHS[0:3] < 20V) with 28W bit=0(15) Output Current 5.0A Current Sense Ratio (CSR1) Accuracy (6.0V < VHS[0:3] < 20V) with 28W bit=0 Output Current 12.5A 75A Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 5.0A with CSR0 ratio OFF Open-load Detection Source Current(16) IOLD(OFF) VOLD(THRES) IOLD(ON) IOLD(ON_LED) 2.5 VOSD(THRES) VPWR-1.2 VPWR-0.8 VCL - 22 TSD 155 - 175 -16 195 VPWR-0.4 V 5.0 10 V VCL(CSNS) VDD+0.25 30 2.0 100 - 3.0 300 VDD+1.0 100 4.0 600 A V mA mA CSR1_0_ACC -17 -12 - - +17 +12 V Symbol Min Typ Max Unit (CSR0_0)/ (T) 0.04 %/C % OFF Open-load Fault Detection Voltage Threshold ON Open-load Fault Detection Current Threshold ON Open-load Fault Detection Current Threshold with LED VHS[0:3] = VPWR - 0.75V Output Short to VPWR Detection Voltage Threshold Output programmed OFF Output Negative Clamp Voltage 0.5A < IHS[0:3] < 5.0A, Output programmed OFF Output Over-temperature Shutdown for 4.5V < VPWR < 28V C Notes 15. Based on statistical data: delta(CSR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production tested. 16. Output OFF Open-Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES) 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS www..com Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic CONTROL INTERFACE Input Logic High Voltage(17) Input Logic Low Voltage(17) (20) Symbol Min Typ Max Unit VIH VIL IDWN IUP CSO RDWN (21) 2.0 -0.3 5.0 5.0 - 125 - - - - - - 250 4.0 VDD+0.3 0.8 20 20 20 500 12 V V A A pF k pF V Input Logic Pull-down Current (SCLK, SI) Input Logic Pull-up Current (CS) SO, FS Tri-state Capacitance(18) Input Logic Pull-down Resistor (RST, WAKE and IN[0:3]) Input Capacitance (18) (19) CIN VCL(WAKE) Wake Input Clamp Voltage ICL(WAKE) < 2.5mA 18 VF(WAKE) - 2.0 VSOH VDD-0.4 VSOL - ISO(LEAK) - 2.0 25 32 V Wake Input Forward Voltage ICL(WAKE) = -2.5mA SO High state Output Voltage IOH = 1.0mA SO and FS Low state Output Voltage IOL = -1.0mA SO, CSNS and FS Tri-state Leakage Current CS = VIH and 0 V < VSO < VDD, or FS = 5.5V, or CSNS=0.0V - - 0.3 V - - V - 0.4 A 0 2.0 k FSI External Pull-down Resistance(22) Watchdog Disabled Watchdog Enabled RFS - 10 0 Infinite 1.0 - Notes 17. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 18. 19. 20. 21. 22. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0V. Pull-down current is with VSI > 1.0V and VSCLK > 1.0V. Pull-up current is with VCS < 2.0V. CS has an active internal pull-up to VDD. In Fail-safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to VREG ~ 3.0V. 10XS3412 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUT TIMING HS0 TO HS3 Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(23) VPWR = 14V Output Rising Slow Slew Rate (low speed slew rate / SR[1:0]=01)(23) VPWR = 14V Output Falling Fast Slew Rate (high speed slew rate / VPWR = 14V Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(23) VPWR = 14V Output Falling Slow Slew Rate (low speed slew rate / SR[1:0]=01)(23) VPWR = 14V Output Rising Fast Slew Rate (high speed slew rate / SR[1:0]=10)(23) VPWR = 14V HS[0,1] Output Turn-ON and Turn-OFF Delay Times(24) VPWR = 14V HS[2,3] Output Turn-ON and Turn-OFF Delay Times(24) VPWR = 14V Driver Output Matching Slew Rate (SRR /SRF) VPWR = 14V @ 25C and for medium speed slew rate (SR[1:0]=00) Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) VPWR = 14V, f PWM = 240Hz, PWM duty cycle = 50%, @ 25C for medium speed slew rate (SR[1:0]=00) t RF -25 -5.0 15 SR 0.8 1.0 1.2 s t DLY_01 SRF_10 0.3 45 0.6 70 1.2 95 s SRF_01 0.07 0.15 0.3 V/s SRF_00 0.15 0.3 0.6 V/s SR[1:0]=10)(23) SRR_10 0.3 0.6 1.2 V/s SRR_01 0.07 0.15 0.3 V/s SRR_00 0.15 0.3 0.6 V/s V/s Symbol Min Typ Max Unit t DLY_23 40 65 90 s Notes 23. Rise and Fall Slew Rates measured across a 5.0 resistive load at high side output = 30% to 70% (see Figure 4, page 19). 24. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3] and CS) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with RL = 5.0 resistive load. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3] and CS) that would turn the output OFF to VHS[0 : 3] =VPWR / 2 with RL = 5.0 resistive load. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) Fault Detection Blanking Time(25) Output Shutdown Delay CSNS Valid Time (27) (28) Symbol Min Typ Max Unit tFAULT tDETECT - - - 217 105 5.0 7.0 70 310 150 20 30 100 400 195 s s s ms ms ms Time(26) t CNSVAL t WDTO TOLD(LED) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 Watchdog Timeout ON Open-load Fault Cyclic Detection Time with LED Output Over-current Time Step for 28W bit = 0 OC[1:0]=00 (slow by default) 4.40 1.62 2.10 2.88 4.58 10.16 73.2 1.10 0.40 0.52 0.72 1.14 2.54 18.2 2.20 0.81 1.05 1.44 2.29 5.08 36.6 8.8 3.2 4.2 5.7 9.1 20.3 146.4 6.30 2.32 3.00 4.12 6.56 14.52 104.6 1.57 0.58 0.75 1.03 1.64 3.63 26.1 3.15 1.16 1.50 2.06 3.28 7.26 52.3 12.6 4.6 6.0 8.2 13.1 29.0 209.2 8.02 3.00 3.90 5.36 8.54 18.88 134.0 2.00 0.75 0.98 1.34 2.13 4.72 34.0 4.01 1.50 1.95 2.68 4.27 9.44 68.0 16.4 21.4 7.8 10.7 17.0 37.7 272.0 OC[1:0]=01 (fast) tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 OC[1:0]=10 (medium) tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 OC[1:0]=11 (very slow) tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 Notes 25. Time necessary to report the fault to FS pin. 26. Time necessary to switch off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage = 50% of VPWR 27. 28. Time necessary for CSNS to be within 5% of the targeted value (from HS voltage = 50% of VPWR to 5% of the targeted CSNS value). For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding input command. 10XS3412 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Output Over-current Time Step for 28W bit = 1 OC[1:0]=00 (slow by default) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 OC[1:0]=01 (fast) tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 OC[1:0]=10 (medium) tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 OC[1:0]=11 (very slow) tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 3.4 1.1 1.4 2.0 3.4 8.5 62.4 0.86 0.28 0.36 0.51 0.78 2.14 20.2 1.7 0.5 0.7 1.0 1.7 4.2 31.2 6.8 2.2 2.9 4.0 6.8 17.0 124.8 4.9 1.6 2.1 2.9 4.9 12.2 89.2 1.24 0.40 0.52 0.74 1.12 3.06 22.2 2.5 0.8 1.0 1.5 2.5 6.1 44.6 9.8 3.2 4.2 5.8 9.8 24.4 178.4 6.4 2.1 2.8 3.8 6.4 15.9 116.0 1.61 0.52 0.68 0.96 1.46 3.98 28.9 3.3 1.0 1.3 2.0 3.3 6.0 58.0 12.8 16.7 5.5 7.6 12.8 31.8 232.0 Symbol Min Typ Max Unit ms 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Bulb Cooling Time Step for 28W bit = 0 CB[1:0]=00 or 11 (medium) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 CB[1:0]=01 (fast) tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 CB[1:0]=10 (slow) tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 for 28W bit = 1 CB[1:0]=00 or 11 (medium) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 CB[1:0]=01 (fast) tBC6_00 tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 CB[1:0]=10 (slow) tBC6_01 tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 291 156 178 208 251 314 146 78 88 101 126 226 583 312 357 417 501 628 417 224 255 298 359 449 209 112 127 145 180 324 834 448 510 596 717 898 542 292 332 388 467 584 272 146 166 189 234 422 1085 582 665 775 933 1170 tBC6_10 484 252 280 316 362 422 694 362 400 452 518 604 1904 472 520 588 674 786 242 126 140 158 181 211 121 63 70 79 90 105 347 181 200 226 259 302 173 90 100 113 129 151 452 236 260 294 337 393 226 118 130 147 169 197 Symbol Min Typ Max Unit ms 10XS3412 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic PWM MODULE TIMING Input PWM Clock Range on IN0 Input PWM Clock Low Frequency Detection Range on IN0(29) Input PWM Clock High Frequency Detection Range on IN0(29) Output PWM Frequency Range Output PWM Frequency Accuracy using Calibrated Oscillator Default Output PWM Frequency using Internal Oscillator CS Calibration Low Minimum Time Detection Range CS Calibration Low Maximum Tine Detection Range Symbol Min Typ Max Unit fIN0 fIN0(LOW) fIN0(HIGH) fPWM AFPWM(CAL) fPWM(0) t CSB(MIN) t CSB(MAX) RPWM_1k RPWM_400 RPWM_200 7.68 1.0 100 - -10 84 14 140 6.0 10 5.0 - 2.0 200 - - 120 20 200 - 51.2 4.0 400 1.0 +10 156 26 260 94 98 98 kHz kHz kHz kHz % Hz s s % % % Output PWM Duty-Cycle Range for fpwm = 1.0kHz for High Speed Slew Rate(30) Output PWM Duty-Cycle Range for fpwm = 400Hz(30) Output PWM Duty-Cycle Range for fpwm = 200Hz INPUT TIMING Direct Input Toggle Timeout AUTORETRY TIMING Autoretry Period TEMPERATURE ON THE GND FLAG Thermal Prewarning Detection(31) Analog Temperature Feedback at TA = 25C with RCSNS=2.5k Analog Temperature Feedback Derating with RCSNS=2.5k (32) (30) tIN tAUTO TOTWAR TFEED DTFEED 175 250 325 ms 105 150 195 ms 110 1.15 -3.5 125 1.20 -3.7 140 1.25 -3.9 C V mV/C Notes 29. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0]. 30. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle 100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming and the PWM on the output with RL = 5.0 resistive load. 31. 32. Typical value guaranteed per design. Value guaranteed per statistical analysis. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS www..com Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V VPWR 20V, 3.0V VDD 5.5V, - 40C TA 125C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic SPI INTERFACE CHARACTERISTICS(33) Maximum Frequency of SPI Operation Required Low State Duration for RST(34) (35) (35) Symbol Min Typ Max Unit f SPI t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI (SU) t SI (HOLD) t RSO - 10 - - - - - - - - - - - - - - - - - - 8.0 - 1.0 5.0 500 50 50 60 37 49 MHz s s s ns ns ns ns ns ns ns Rising Edge of CS to Falling Edge of CS (Required Setup Time) Rising Edge of RST to Falling Edge of CS (Required Setup Time) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(35) (35) Required High State Duration of SCLK (Required Setup Time) Required Low State Duration of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Setup SO Rise Time CL = 80pF SO Fall Time CL = 80pF SI, CS, SCLK, Incoming Signal Rise Time(36) SI, CS, SCLK, Incoming Signal Fall Time (36) (36) (35) Time)(35) Time)(36) - - 13 ns t FSO - - - - - - 13 13 13 60 60 t RSI t FSI t SO(EN) t SO(DIS) - - - - ns ns ns ns Time from Rising Edge of SCLK to SO Low Time from Rising Edge of SCLK to SO High Notes 33. 34. 35. 36. 37. 38. Parameters guaranteed by design. Impedance(37) Impedance(38) RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 10XS3412 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0k on pullup on CS. Time required for output status data to be terminated at SO. 1.0k on pullup on CS. 10XS3412 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS www..com TIMING DIAGRAMS IN[0:3] high logic level low logic level CS high logic level low logic level VHS[0:3] VPWR RPWM 50%VPWR Time or Time Time VHS[0:3] 70% VPWR 30% VPWR t DLY(ON) t DLY(OFF) SR F Time SR R Figure 4. Output Slew Rate and Time Delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5. Over-current Shutdown Protection 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS www..com IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 tB C1 t BC2 t BC3 t BC4 tB C5 tB C6 Previous OFF duration (toff) Figure 6. Bulb Cooling Management VIH VIH RSTB RST 10% V 0.2 VDD DD tWRST TwRSTB tENBL TCSB t CS VIL VIL TENBL 90% VDD 0.7VDD CS CSB 10% VDD 0.7VDD VIH VIH VIL VIL tTlead LEAD t WSCLKh TwSCLKh t RSI TrSI SCLK SCLK 90% VDD 0.7VDD 10% VDD 0.2VDD t LAG Tlag VIH VIH VIL VIL t TSIsu SI(SU) t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) tTfSI FSI Valid Don't Care VIH VIH SI SI Don't Care 90% VDD 0.7 VDD 0.2VDD 10% VDD Valid Don't Care VIH VIL Figure 7. Input Timing Switching Characteristics 10XS3412 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS www..com tRSI TrSI 90% VDD 3.5V tFSI TfSI VOH VOH 50% 1.0V 10% VDD VOL VOL SCLK SCLK t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD VOH VOH VOL VOL 0.2 VDD DD 10% V TrSO t RSO TVALID t VALID Low-to-High Low to High SO SO 90% V High to Low High-to-Low 0.7 VDD DD TfSO t FSO VOH VOH TdlyHL t SO(DIS) 0.2VDD 10% VDD VOL VOL Figure 8. SCLK Waveform and Valid SO Data Delay Time 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DESCRIPTION INTRODUCTION www..com FUNCTIONAL DESCRIPTION INTRODUCTION The 10XS3412 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(ON) MOSFETs (dual 10m, dual 12m) can control four separate 55W / 28W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slewrate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 10XS3412 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The Current Sense pin provides a current proportional to the designated HS0 : HS3 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resistor (4.7k typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through SPI. DIRECT INPUTS (IN0, IN1, IN2, IN3) Each IN input wakes the device. The IN0 : IN3 high side input pins are also used to directly control HS0 : HS3 high side output pins. In case of the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, RDWN. the device is capable of transferring information to, and receiving information from, the MCU. The 10XS3412 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pull-up from VDD, IUP. SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 10XS3412 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 9, page 25). SCLK input has an active internal pulldown, IDWN. FAULT STATUS (FS) This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin. WAKE The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10k typ). This input has a passive internal pulldown, RDWN. SERIAL INPUT (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XS3412 are configured and controlled using a 5-bit addressing scheme described in Table 9, page 34. Register addressing and configuration are described in Table 10, page 34. SI input has an active internal pull-down, IDWN. RESET (RST) The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep Mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN. DIGITAL DRAIN VOLTAGE (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe Mode. CHIP SELECT (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, 10XS3412 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION www..com GROUND (GND) These pins are the ground for the device. HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 10m and 12m high side power outputs to the load. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. FAIL-SAFE INPUT (FSI) This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature. When the FSI pin is opened, the watchdog circuit is enabled. After a Watchdog timeout occurs, the output states depends on IN[0:3]. When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:3] in case of VDD Failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]). SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in Table 22, page 38. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION www..com FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC10XS3412 - Functional Block Diagram Self-protected High Side Switches Power Supply MCU Interface and Output Control Parallel Control Inputs SPI Interface PWM Controller Power Supply MCU Interface and Output Control HS0 - HS3 Self-protected High Side Switches POWER SUPPLY The 10XS3412B is designed to operate from 4.0V to 28V on the VPWR pin. Characteristics are provided from 6.0V to 20V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep Mode. Applying VPWR and VDD to the device will place the device in the Normal Mode. The device will transit to Fail-safe Mode in case of failures on the SPI or/and on VDD voltage. loads demanding multiple switching, an external recirculation device must be used to maintain the device in its Safe Operating Area. MCU INTERFACE AND OUTPUT CONTROL In Normal Mode, each bulb is controlled directly from the MCU through SPI. A pulse width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100Hz to 400Hz) and addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault conditions are: open load, short circuit to battery, short circuit to ground (over-current and severe short-circuit), thermal shutdown, and under/overvoltage. Thanks to accurate and configurable over-current detection circuitry and wire-harness optimization, the vehicle is lighter. In Fail-safe Mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode. HIGH SIDE SWITCHES: HS0 - HS3 These pins are the high side outputs controlling automotive lamps located for the front of vehicle, such as 65W/55W bulbs and Xenon-HID modules. Those N-channel MOSFETs with 10m & 12m RDS(ON) are self-protected and present extended diagnostics in order to detect bulb outage and short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. When driving DC motor or Solenoid 10XS3412 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION www..com FUNCTIONAL DEVICE OPERATION SPI PROTOCOL DESCRIPTION The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI / SO pins of the 10XS3412 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0V or 3.3V CMOS logic levels. CSB CS CS SCLK SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Notes 1. RST is a logic [1] state during the above operation. NOTES: 1. 2. D15:D0 relate state during therecent ordered entry of data into the device. RSTB is in a logic H to the most above operation. out of 2. 3. OD15:OD0 and D15to the firstmostbits ofordered entry of program data into the LUX IC the device. DO, D1, D2, ... , relate relate to the 16 recent ordered fault and status data device. Figure 9. Single 16-Bit Word SPI Communication 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES www..com OPERATIONAL MODES The 10XS3412 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 5 and Figure 11 summarize details contained in succeeding paragraphs. The Figure 10 describes an internal signal called IN_ON[x] depending on IN[x] input. tIN Table 5. 10XS3412 Operating Modes Mode Sleep Normal wake-up 0 1 fail fault x 0 x 0 Comments Device is in Sleep Mode. All outputs are OFF. Device is currently in Normal Mode. Watchdog is active if enabled. Device is currently in Fail-safe mode due to watchdog timeout or VDD Failure conditions. The output states depend on the corresponding input in case the FSI is open. Device is currently in Fault Mode. The faulted output(s) is (are) OFF. The safe autoretry circuitry is active to turn-on again the output(s). IN[x] IN_ON[x] Fail-Safe 1 1 0 Figure 10. IN_ON[x] internal signal The 10XS3412 transits to operating modes according to the following signals: * wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3], * fail = (VDD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground), * fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and OV_dis). Fault 1 X 1 x = Don't care. (wake-up=0) (wake-up=1) and (fail=1) and (fault=0) (wake-up=0) (fail=1) and (wake-up=1) and (fault=1) Sleep (fail=0) and (wake-up=1) and (fault=0) (wake-up=1) and (fault=1) (wake-up=0) Fault (fail=0) and (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=0) Normal Fail-Safe (fail=1) and (wake-up=1) and (fault=0) (fail=0) and (wake-up=1) and (fault=0) (fail=1) and (wake-up=1) and (fault=0) Figure 11. Operating Modes 10XS3412 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES www..com SLEEP MODE The 10XS3412 is in Sleep Mode when: * VPWR and VDD are within the normal voltage range, * wake-up = 0, * fail = X, * fault = X. This is the Default Mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST and IN_ON[0:3] are logic [0]. In the Sleep Mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0]. In the event of an external VPWR supply disconnect, an unexpected current consumption may sink on the VDD supply pin (In Sleep State). This current leakage is about 70mA instead of 5.0A and it may impact the device reliability. The device recovers its normal operational mode once VPWR is reconnected. To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal Mode with RST pin set to logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0V on VDD supply pin to switch the device to Sleep State. the range of 5% to 98% with a resolution of 7 bits of duty cycle (Table 6). The state of other IN pin is ignored. Table 6. Output PWM Resolution On bit 0 1 1 1 1 1 Duty cycle X 0000000 0000001 0000010 n 1111111 Output state OFF PWM (1/128 duty cycle) PWM (2/128 duty cycle) PWM (3/128 duty cycle) PWM ((n+1)/128 duty cycle) fully ON The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module (Table 7). Table 7. Output PWM Switching Delay Delay bits 000 001 010 011 100 101 110 111 Output delay no delay 16 PWM clock periods 32 PWM clock periods 48 PWM clock periods 64 PWM clock periods 80 PWM clock periods 96 PWM clock periods 112 PWM clock periods NORMAL MODE The 10XS3412 is in Normal Mode when: * VPWR and VDD are within the normal voltage range, * wake-up = 1, * fail = 0, * fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]). Programmable PWM module The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1]. The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The outputs HS[0:3] can be controlled in The clock frequency from IN0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. Calibratable internal clock The internal clock can vary as much as +/-30 percent corresponding to typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XS3412 allows clock period setting within +/-10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CS pin after the SPI word is launched. At the moment, the CS pin transitions from logic [1] to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES www..com CS During the Fail-safe Mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value (except POR bit) and fault protections are fully operational. The Fail-safe Mode can be detected by monitoring the NM bit is set to [0]. CALR SI command ignored SI NORMAL & FAIL-SAFE MODE TRANSITIONS Transition Fail-Safe to Normal mode To leave the Fail-safe Mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to logic [1] ; the other bits are not considered. The previous latched faults are reset by the transition into Normal Mode (autoretry included). Moreover, the device can be brought out of the Fail-safe Mode due to watchdog timeout issue by forcing the FSI pin to logic [0]. Transition Normal to Fail-safe Mode To leave the Normal Mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-safe Mode (autoretry included). Internal clock duration In case of negative CS pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored and the internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before. The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1]. FAIL-SAFE MODE The 10XS3412 is in Fail-safe Mode when: * VPWR is within the normal voltage range, * wake-up = 1, * fail = 1, * fault = 0. Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:3] or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), the device will operate normally. Fail-Safe conditions If an internal watchdog timeout occurs before the WD bit for FSI open (Table 8) or in case of VDD failure condition (VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe Mode until the WD bit is written to logic [1] (see Fail-safe to Normal Mode transition paragraph) and VDD is within the normal voltage range. Table 8. SPI Watchdog Activation Typical RFSI () 0 (shorted to ground) (open) Watchdog Disabled Enable FAULT MODE The 10XS3412 is in Fault Mode when: * VPWR and VDD are within the normal voltage range * wake-up = 1 * fail = X * fault=1 This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up: * Over-temperature fault * Over-current fault * Severe short-circuit fault * Output(s) shorted to VPWR fault in OFF state * Open load fault in OFF state * Over-voltage fault (enabled by default) * Under-voltage fault The FS pin will automatically return to logic [1] when the fault condition is removed, except for over-current, severe short-circuit, over-temperature and under-voltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS pin. 10XS3412 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES www..com START-UP SEQUENCE The 10XS3412 enters in Normal Mode after start-up if following sequence is provided: *VPWR and VDD power supplies must be above their under-voltage thresholds, *generate wake-up event (wake-up=1) from 0 to 1 on RST. The device switches to Normal Mode with SPI register content is reset (as defined in Table 10 and Table 22). All features of the 10XS3412 will be available after 50s typical and all SPI registers are set to default values (set to logic [0]). The UV fault is reported in the SPI status registers. And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock: *apply PWM clock on IN0 input pin after maximum 200s (min. 50s). If the correct start-up sequence is not provided, the PWM function is not guaranteed. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES www..com PROTECTION AND DIAGNOSTIC FEATURES PROTECTIONS Over-temperature Fault The 10XS3412 incorporates over-temperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: *If the output command is ON: the corresponding output is latched OFF. FS will be also latched to logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. *If the output command is OFF: FS will go to logic [0] till the corresponding output temperature will be below TSD. For both cases, the fault register OT[0:3] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after a SPI read command. Over-current Fault The 10XS3412 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition. This protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55W or 28W bulb profiles, selectable separately by Xenon bit and 28W bits (as illustrated Figure 13, page 36). In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an autoretry define this event. In this case, the over-current protection will be fitted to inrush current, as shown in Figure 5. This over-current protection is programmable: OC[1:0] bits select over-current slope speed and OCHI1 current step can be removed in case of OCHI bit is set to [1]. levels are available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits. If the load current level ever reaches the over-current detection level, the corresponding output will latch the output OFF and FS will be also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (OC[0:3] bits) is removed after a read operation. In Normal Mode using internal PWM module, the 10XS3412 incorporates also a cooling bulb filament management if OC_mode and Xenon are set to logic [1]. In this case, the 1st step of multi-step over-current protection will depend to the previous OFF duration, as illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits. Depending on toff depending to toff Over-current thresholds Cooling toff fault_control hson signal hson PWM Over-current thresholds Severe Short-Circuit Fault The 10XS3412 provides output shutdown in order to protect each output in case of severe short-circuit during of the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FS will go to logic [0] and the fault register SC[0:3] bit will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. fault_control hson signal hson PWM In steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC over-current 10XS3412 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES www..com The SPI fault report (SC[0:3] bits) is removed after a read operation. Over-voltage Fault (Enabled by default) By default, the over-voltage protection is enabled. The 10XS3412 shuts down all outputs and FS will go to logic [0] during an over-voltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the over-voltage condition is removed (VPWR < VPWR(OV) VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. The over-voltage protection can be disabled through SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any over-voltage condition (VPWR > VPWR(OV)). This over-voltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold. In Fail-safe Mode, the over-voltage activation depends on the RST logic state: enable for RST = 1 and disable for RST = 0. The device is still protected with over-temperature protection in case the over-voltage feature is disabled. Under-voltage Fault The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the internal logic states within the device will remain (configuration and reporting). In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FS will go to logic [0], and the fault register UV bit will be set to [1]. Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP): *If outputs command are low, FS will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning report). *If the output command is ON, FS will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the VPWR voltage does not drop any lower than 3.5V typical. All latched faults (over-temperature, over-current, severe short-circuit, over and under-voltage) are reset if: * VDD < VDD(FAIL) with VPWR in nominal voltage range, *VDD and VPWR supplies is below VSUPPLY(POR) voltage value. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES www..com (fault_control=0) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (fault_control=1 and OV=0) (OpenloadON=1) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (SC=1) OFF if hson=0 (fault_control=0 or OV=1) ON if hson=1 Latched OFF (fault_control=0) (Retry=1) (count=16) (SC=1) (OpenloadON=1) (after Retry Period and OV=0) Autoretry OFF (OV=1) Autoretry ON if hson=1 (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (fault_control=0) (Retry=1) => count=count+1 Figure 12. Auto-retry State Machine AUTO-RETRY The auto-retry circuitry is used to reactivate the output(s) automatically in case of over-current or over-temperature or under-voltage failure conditions to provide a high availability of the load. Auto-retry feature is available in Fault Mode. It is activated in case of internal retry signal is set to logic [1]: retry[x] = OC[x] or OT[x] or UV. The feature retries to switch-on the output(s) after one auto-retry period (tAUTO) with a limitation in term of number of occurrence (16 for each output). The counter of retry occurrences is reset in cases of mode transitions (refer to NORMAL & FAIL-SAFE MODE TRANSITIONS) and Retry_dis bit toggling. At each auto-retry, the over-current detection will be set to default values in order to sustain the inrush current. The Figure 12 describes the auto-retry state machine. (OFF). The output shorted to VPWR fault is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OS[0:3] and OL_OFF[0:3] fault bits are set in the status register and FS pin reports in real time the fault. If the output shorted to VPWR fault is removed, the status register will be cleared after reading the register. The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:3] bit). Open-Load Faults The 10XS3412 incorporates three dedicated open-load detection circuitries on the output to detect in OFF and in ON state. Open-load Detection In Off State The OFF output open-load fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output open-load fault is latched into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:3] fault bit is set in the status register. If the open load fault is removed (FS output pin goes to high), the status register will be cleared after reading the register. The OFF output open-load protection can be disabled through SPI (OLOFF_DIS[0:3] bit). DIAGNOSTIC Output Shorted to VPWR Fault The 10XS3412 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if output voltage is higher than VOSD(THRES) and reported as a fault condition when the output is disabled 10XS3412 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES www..com Open-load Detection In On State The ON output open-load current thresholds can be chosen by SPI to detect a standard bulbs or LEDs (OLLED[0:3] bit set to logic [1]). In the cases where load current drops below the defined current threshold, OLON bit is set to logic [1], and the output stays ON and FS will not be disturbed. Open-load Detection In On State For Led Open load for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in fully-on state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and SPI read operation is needed (OL_ON[0:3] bit). The ON output open-load protection can be disabled through SPI (OLON_DIS[0:3] bit). Analog Current Recopy and Temperature Feedbacks The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum current is 2mA typical. The typical value of external CSNS resistor connected to the ground is 4.7k. The current recopy is not active in Fail-safe Mode. Temperature Prewarning Detection In Normal Mode, the 10XS3412 provides a temperature prewarning reported via SPI in case of the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed. mode. No additional passive components are required except on VDD current path. GROUND DISCONNECT PROTECTION In the event the 10XS3412 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection (maximum VPWR=16V). A 10k resistor needs to be added between the MCU and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings. LOSS OF SUPPLY LINES Loss of VDD If the external VDD supply is disconnected (or not within specification: VDD ACTIVE CLAMP ON VPWR The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of overload on an output the corresponding output is turned off which leads to a highvoltage at VPWR with an inductive VPWR line. When VPWR voltage exceeds VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:3] outputs are switched ON automatically to demagnetize the inductive Battery line. EMC PERFORMANCES All following tests are performed on Freescale evaluation board in accordance with the typical application schematic. The device is protected in case of positive and negative transients on the VPWR line (per ISO 7637-2). REVERSE BATTERY ON VPWR The output survives the application of reverse voltage as low as -18V. Under these conditions, the ON resistance of the output is 2 times higher than typical ohmic value in forward 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com The 10XS3412 successfully meets the Class 5 of the CISPR25 emission standard and 200V/m or BCI 200mA injection level for immunity tests. LOGIC COMMANDS AND REGISTERS SERIAL INPUT COMMUNICATION SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14 : D13. The next three bits, D12: D10, are used to select the command register. The remaining nine bits, D8 : D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 10XS3412 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10 summarizes the SI registers. Table 9. SI Message Bit Assignment Bit Sig MSB SI Msg Bit D15 D14 : D13 D12 : D10 D9 LSB D8:D0 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. Register address bits used in some cases for output selection (Table 12). Register address bits. Not used (set to logic [0]). Used to configure the inputs, outputs, and the device protection features and SO status content. Table 10. Serial Input Address and Configuration Bit Map SI Data SI Register D15 WDI N D1 D1 D1 D1 D13 D9 4 2 1 0 X A1 A1 A1 A1 0 0 0 X A0 A0 A0 A0 0 0 0 0 0 0 0 1 1 1 X 0 0 1 1 0 0 1 X 0 1 0 1 0 1 1 X 0 0 0 0 0 0 0 0 D8 0 28W_s 0 0 Xenon_ s D7 0 ON_s 0 0 BC1_s D6 0 PWM6_s 0 D5 0 PWM5_s DIR_dis_s D4 SOA4 PWM4_s SR1_s D3 SOA3 PWM3_s SR0_s D2 SOA2 PWM2_s DELAY2_s D1 SOA1 PWM1_s DELAY1_s D0 SOA0 PWM0_s DELAY0_s STATR_s PWMR_s WDI N CONFR0_ WDI s N CONFR1_ WDI s N OCR_s GCR CALR Register state after RST=0 or VDD(FAIL) or VSUPPLY(P condition OR) Retry_ Retry_dis_s OS_dis_s OLON_dis_s OLOFF_dis_ OLLED_en CSNS_ratio s _s _s unlimited_s BC0_s OC1_s OC0_s CSNS_en 1 0 OCHI_s CSNS1 1 0 OCLO1_s CSNS0 0 0 OCLO0_s X 1 0 OC_mode_ s OV_dis 1 0 WDI N WDI N WDI N 0 VDD_F PWM_en CLOCK_sel TEMP_en AIL_en 1 0 0 0 1 0 0 0 x = Don't care. s = Output selection with the bits A1A0 as defined in Table 11. 10XS3412 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com DEVICE REGISTER ADDRESSING The following section describes the possible register addresses (D[14:10]) and their impact on device operation. default value [00] corresponds to the medium speed slew rate (Table 12). Table 12. Slew Rate Speed Selection SR1_s (D4) 0 0 1 1 SR0_s (D3) 0 1 0 1 Slew Rate Speed medium (default) low high Not used ADDRESS XX000 -- STATUS REGISTER (STATR_S) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR and CALR registers (Refer to the section entitled Serial Output Communication (Device Status Return Data) on page 37. Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as shown Table 7, page 27 (only available for PWM_en bit is set to logic [1]). ADDRESS A1A0001-- OUTPUT PWM CONTROL REGISTER (PWMR_S) The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output "s" is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). Table 11. Output Selection A1 (D14) 0 0 1 1 A0 (D13) 0 1 0 1 HS Selection HS0 (default) HS1 HS2 HS3 ADDRESS A1A0011 -- OUTPUT CONFIGURATION REGISTER (CONFR1_S) The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output "s" is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). A logic [1] on bit D6 (RETRY_unlimited_s) disables the autoretry counter for the selected output, the default value [0] corresponds to enable auto-retry feature without time limitation. A logic [1] on bit D5 (RETRY_dis_s) disables the autoretry for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D3 (OLON_dis_s) disables the ON output open-load detection for the selected output, the default value [0] corresponds to enable this feature (Table 13). A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output open-load detection for the selected output, the default value [0] corresponds to enable this feature. A logic [1] on bit D1 (OLLED_en_s) enables the ON output open-load detection for LEDs for the selected output, the default value [0] corresponds to ON output open-load detection is set for bulbs (Table 13). Table 13. ON Open-load Selection OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection 0 0 1 0 1 X enable with bulb threshold (default) enable with LED threshold disable A logic [1] on bit D8 (28W_s) selects the 28W over-current protection profile: the over-current thresholds are divided by 2 and, the inrush and cooling responses are dedicated to 28W lamp. Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down). Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 6, page 27. ADDRESS A1A0010-- OUTPUT CONFIGURATION REGISTER (CONFR0_S) The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output "s" is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable the output from direct control (in this case, the output is only controlled by On bit). D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is the low ratio (Table 14). Table 14. Current Sense Ratio Selection CSNS_high_s (D0) 0 1 Current Sense Ratio CRS0 (default) CRS1 D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 15 and Table 16. . Table 15. Cooling Curve Selection BC1_s (D7) 0 0 1 1 BC0_s (D6) 0 1 0 1 Profile Curves Speed medium (default) slow fast medium ADDRESS A1A0100 -- OUTPUT OVER-CURRENT REGISTER (OCR) The OCR_s register allows the MCU to configure corresponding output over-current protection through the SPI. Each output "s" is independently selected for configuration based on the state of the D14 : D13 bits (Table 11). A logic [1] on bit D8 (Xenon_s) enables the bulb overcurrent profile, as described Figure 13. Table 16. Inrush Curve Selection OC1_s (D5) 0 0 1 OC0_s (D4) 0 1 0 1 Profile Curves Speed slow (default) fast medium very slow Xenon bit set to logic [0]: IOCH1 IOCH2 IOC1 IOC2 IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 1 A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 14. IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t t OC4 OC5 t OC2 t OC6 t OC7 Time Xenon bit set to logic [1]: IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t t OC4 OC5 t OC2 t OC6 t OC7 Time Figure 14. Over-current profile with OCHI bit set to `1' The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17. Table 17. Output Steady State Selection OCLO1 (D2) OCLO0 (D1) t OC6 t OC7 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t t OC4 OC5 t OC2 Steady State Current OCLO2 (default) OCLO3 OCLO4 OCLO1 Time 0 0 1 1 0 1 0 1 Figure 13. Over-current profile depending on Xenon bit 10XS3412 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com Bit D0 (OC_mode_sel) allows to select the over-current mode, as described Table 18. Table 18. Over-current Mode Selection OC_mode_s (D0) 0 1 Over-current Mode only inrush current management (default) inrush current and bulb cooling management Table 21. Output Current Recopy Selection 1 1 HS3 The GCR register disables the over-voltage protection (D0). When this bits is [0], the over-voltage is enabled (default value). ADDRESS 00111 -- CALIBRATION REGISTER (CALR) The CALR register allows the MCU to calibrate internal clock, as explained in Figure 12. ADDRESS 00101 -- GLOBAL CONFIGURATION REGISTER (GCR) The GCR register allows the MCU to configure the device through the SPI. Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows transitioning to Fail-safe Mode for VDD < VDD(FAIL). Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:3] with PWMR register (the direct input states are ignored). Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19. Table 19. PWM Module Selection PWM_en (D7) CLOCK_sel (D6) 0 1 1 X 0 1 PWM module PWM module disabled (default) PWM module enabled with external clock from IN0 PWM module enabled with internal calibrated clock SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA) When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CS transition, is dependent upon the previously written SPI word. Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1 and OCR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous SOA4, SOA3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exception: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * The VPWR voltage is below 4.0V, the status must be ignored by the MCU. Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20. Table 20. CSNS Reporting Selection TEMP_en CSNS_en (D5) (D4) 0 X 1 0 1 0 CSNS reporting CSNS tri-stated (default) current recopy of selected output (D3:2] bits) temperature on GND flag Table 21. Output Current Recopy Selection CSNS1 (D3) 0 0 1 CSNS0 (D2) 0 1 0 CSNS reporting HS0 (default) HS1 HS2 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com SERIAL OUTPUT BIT ASSIGNMENT The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 22, summarizes SO returned data for bits OD15 : OD0. * Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. Table 22. Serial Output Bit Map Description Previous STATR SO SO SO SO SO A4 A3 A2 A1 A0 STATR_s A1 A0 PWMR_s A1 A0 CONFR0 A1 A0 _s CONFR1 A1 A0 _s 0 0 0 0 0 1 OD 15 OD 14 OD 13 OD 12 OD 11 OD OD9 OD8 10 POR OD7 * Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message. * Bit OD9 is set to logic [1] in Normal Mode (NM). * The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 22. SO Returned Data OD6 OD5 OD4 OLOFF_ s OD3 OD2 OD1 OD0 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM UV OV OLON_s OS_s PWM3_s SR0_s OT_s PWM2_s DELAY2_s SC_s PWM1_s DELAY1_s OC_s PWM0_s DELAY0_s 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 28W_s ON_s PWM6_s PWM5_s PWM4_s 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X X DIR_dis_ SR1_s s 0 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM X X Retry_ Retry_dis OS_dis_ _s s unlimited _s BC0_s OC1_s OC0_s OLON_dis_s OLOFF_dis_s OLLED_en_ CSNS_ratio_ s s OCR_s A1 A0 0 0 0 1 0 0 1 0 1 0 0 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM Xenon BC1_s _s OCHI_s OCLO1_s OCLO0_s OC_mode_s GCR DIAGR0 DIAGR1 DIAGR2 1 1 1 1 0 1 1 1 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM VDD_F PWM_ CLOCK_ TEMP_e CSNS_e AIL_en en sel n n 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 1 WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 0 0 0 0 0 0 0 X X X X X X X 0 X X X 0 X X X 0 X IN3 X 0 CSNS1 X IN2 X 0 CSNS0 CLOCK_fail IN1 0 0 X CAL_fail IN0 0 0 OV_dis OTW WD_en 0 0 Register N/A N/A N/A N/A N/A state after RST=0 or VDD(FAIL) or VSUPPLY( conditio n POR) s = Output selection with the bits A1A0 as defined in Table 11 PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000 (STATR_S) The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read operation. Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits SOA4:SOA3 = A1A0 (Table 22). * OC_s: over-current fault detection for a selected output, * SC_s: severe short-circuit fault detection for a selected output, * OS_s: output shorted to VPWR fault detection for a selected output, * OLOFF_s: openload in OFF state fault detection for a selected output, * OLON_s: openload in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output, * OV: over-voltage fault detection, * UV: under-voltage fault detection * POR: power on reset detection. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal). PREVIOUS ADDRESS SOA4 : SOA0 = A1A0001 (PWMR_S) The returned data contains the programmed values in the PWMR register for the output selected with A1A0. 10XS3412 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS www..com PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010 (CONFR0_S) The returned data contains the programmed values in the CONFR0 register for the output selected with A1A0. The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case of Fail-safe state due to watchdog timeout as explained in the following Table 23. Table 23. Watchdog activation report WD_en (OD0) 0 1 SPI Watchdog disabled enabled PREVIOUS ADDRESS SOA4 : SOA0 = A1A0011 (CONFR1_S) The returned data contains the programmed values in the CONFR1 register for the output selected with A1A0. PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100 (OCR_S) The returned data contains the programmed values in the OCR register for the output selected with A1A0. PREVIOUS ADDRESS SOA4 : SOA0 = 10111 (DIAGR2) The returned data is the product ID. Bits OD2:OD0 are set to 000 for Protected Dual 10m and 12m High Side Switches. PREVIOUS ADDRESS SOA4 : SOA0 = 00101 (GCR) The returned data contains the programmed values in the GCR register. DEFAULT DEVICE CONFIGURATION The default device configuration is explained below: * HS output is commanded by corresponding IN input or On bit through SPI. The medium slew rate is used, * HS output is fully protected by the Xenon over-current profile by default, the severe short-circuit protection, the under-voltage and the over-temperature protection. The auto-retry feature is enabled, * Open-load in ON and OFF state and HS shorted to VPWR detections are available, * No current recopy and no analog temperature feedback active, * Over-voltage protection is enabled, * SO reporting fault status from HS0, * VDD failure detection is disabled. PREVIOUS ADDRESS SOA4 : SOA0 = 00111 (DIAGR0) The returned data OD2 reports logic [1] in case of PWM clock on IN0 pin is out of specified frequency range. The returned data OD1 reports logic [1] in case of calibration failure. The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above TOTWAR). PREVIOUS ADDRESS SOA4 : SOA0 = 01111 (DIAGR1) The returned data OD4: OD1 report in real time the state of the direct input IN[3:0]. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 39 TYPICAL APPLICATIONS www..com TYPICAL APPLICATIONS The following figure shows a typical automotive lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22nF decoupling capacitor to the module connector. VPWR VDD Voltage regulator 100nF 10F 100nF 10F VDD VDD VPWR ignition switch VDD VPWR VDD 100nF WAKE VPWR 100nF 100nF 10k VDD I/O 10k MCU SCLK CS I/O SO SI A/D 22nF 10k 10k 10k 10k FS IN0 IN1 IN2 IN3 SCLK CS RST SI SO CSNS FSI 4.7k 10k VPWR 10k 10k 10k HS0 22nF LOAD 0 10XS3412 HS1 22nF LOAD 1 HS2 22nF LOAD 2 10k HS3 22nF LOAD 3 GND Watchdog direct light commands (pedal, comodo,...) 10XS3412 40 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOLDERING INFORMATION www..com PACKAGING SOLDERING INFORMATION The 10XS3412 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 10XS3412 was qualified in accordance with JEDEC standards J-STD-020C Sn-Pb reflow profile. The maximum peak temperature during the soldering process should not exceed 245 for 10 seconds maximum duration. The AN2469 provides guidelines for Printed Circuit Board design and assembly. 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 41 PACKAGING PACKAGE DIMENSIONS www..com PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below. PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D 10XS3412 42 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS www..com PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 43 PACKAGING PACKAGE DIMENSIONS www..com PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D Figure 15. Package Mechanical Outline 10XS3412 44 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS www..com PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D Package Mechanical Outline 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 45 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) www..com ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) Introduction This thermal addendum is provided as a supplement to the 10XS3412 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. Package and Thermal Considerations This 10XS3412 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 = 10XS3412PNA 24-PIN PQFN RJA11 RJA12 RJA21 RJA22 . P1 P2 PNA SUFFIX (PB-FREE) 98ARL10596D 24-PIN PQFN (12 x 12) Note For package dimensions, refer to the 10XS3412 data sheet. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 24. Thermal Performance Comparison Thermal Resistance RJAmn (1)(2) RJBmn (2)(3) RJAmn (1)(4) RJCmn (5) 1 = Power Chip, 2 = Logic Chip [C/W] m = 1, n=1 26.04 13.21 46.42 0.67 m = 1, n = 2 m = 2, n = 1 18.18 6.40 37.03 0.95 m = 2, n=2 35.49 23.94 53.82 0.00 0.2mm 0.5mm dia. 0.2mm Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad. Figure 16. Detail of Copper Traces Under Device with Thermal Vias 10XS3412 46 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) www..com 76.2mm 76.2mm 114.3mm Figure 17. 1s JEDEC Thermal Test Board Layout Figure 18. 2s2p JDEC Thermal Test Board (Red - Top Layer, Yellow - Two Buried Layers) WAKE CSNS SCLK VDD RST IN3 IN2 IN1 Transparent Top View 13 12 11 10 SO GND 16 17 14 GND 9 8 7 6 5 4 3 2 1 24 23 FSI GND IN0 NC CS FS SI HS3 18 22 HS2 15 VPWR MC10XS3412 Pin Connections 24-PIN PQFN (12 x 12) 0.9 mm Pitch 12.0mm 12.0mm Body 19 HS1 20 NC 21 HS0 Figure 19. Thermal Test Board 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 114.3mm 47 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) www..com Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness Cu buried traces thickness 0.035mm 76.2mm x 114.3mm board area, including edge connector for thermal testing, 74mm x 74mm buried layers area Cu heat-spreading areas on board surface Natural convection, still air Table 25. Thermal Resistance Performance Thermal Resistance Area A (mm2) 0 150 1 = Power Chip, 2 = Logic Chip (C/W) m = 1, n=1 46.42 41.60 40.02 38.86 38.04 m = 1, n = 2 m = 2, n = 1 37.03 32.90 31.63 30.68 29.99 m = 2, n=2 53.82 51.27 55.05 49.47 48.63 Outline: RJAmn 300 450 600 Area A: Ambient Conditions: RJA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 65.00 Thermal resistance [K/W] 60.00 55.00 50.00 45.00 40.00 35.00 30.00 25.00 0 100 200 300 400 500 600 Heat spreading area [sqmm] RJA11 RJA12=RJA21 RJA22 Figure 20. Steady State Thermal Resistance in Dependance on Heat Streading Area; 1s JEDEC Thermal Test Board with Spreading Areas 10XS3412 48 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0) www..com 100 Thermal Resistance [K/W] 10 1 0.1 0.000001 0.0001 0.01 Time[s] RJA11 RJA12 1 100 10000 RJA22 Figure 21. Transient Thermal 1W Step Response; Device on 1s JEDEC Standard Thermal Test Board with Heat Spreading Areas 600 Sq. mm 100 Thermal resistance [K/W] 10 1 0.1 0.000001 0.0001 0.01 Time [s] RJA11 RJA12 1 100 10000 RJA22 Figure 22. Transient Thermal 1W Step Response; Device on 2s2p JEDEC Standard Thermal Test Board 10XS3412 Analog Integrated Circuit Device Data Freescale Semiconductor 49 REVISION HISTORY www..com REVISION HISTORY REVISION 7.0 8.0 DATE 10/2008 10/2008 DESCRIPTION OF CHANGES * * * Initial release Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5. Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics Table on page 8. 10XS3412 50 Analog Integrated Circuit Device Data Freescale Semiconductor www..com How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. MC10XS3412 Rev. 8.0 10/2008 |
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